1. Field of the Invention
The present invention relates to a circuit arrangement for telecommunication exchange systems, particularly time-division multiplex (TDM) telephone exchange systems, having central control units and sub-central devices which forward information to the respective central control unit and receive information therefrom and which are connected to the central control unit over lines individually associated therewith or over channels with a TDM line individually associated therewith, and in which the central control unit is equipped with an input/output memory and an input/output control device for the information exchange with the sub-central device and for information exchange between sub-central devices.
2. Description of the Prior Art
In centrally-controlled telecommunication exchange systems, the principal of division of control operations to PBX sub-control devices is preferably employed, such as can be derived, for example, from the German published application 28 16 286 and from the art cited therein. In such a system, the transmission of information between a central control unit and each of the sub-control devices, respectively in the one and the other direction, as well as between two of the sub-control devices plays a decisive role. The above publication provides a common data bus for this purpose.
The German Letters Patent No. 11 90 517 provides a central re-transmission control device with a central memory which always first accepts all information to be exchange between the PBX control devices individually from one of the control devices, then intermediately stores the information and subsequently retransmits the same to the appertaining control device. In a manner technically related thereto, the German Letters Patent 28 13 721 provides a plurality of intermediate memories serving the same purpose, of which each can accept information from peripheral control devices and relay the same to a respective sub-control unit. A central bus serves this purpose, and is utilized on a case-by-case basis for information transmission.
The German Letters Patent No. 23 27 669, corresponding to British Specification No. 1,459,621, provides a common data bus for information transmission between a central control unit and sub-control devices (in both direction) as well as between two sub-control devices. The data bus can be seized by the central control unit for information transmission to and from the central control unit. Further, another central distributor is provided which can seize the data bus for information transmissions between two sub-control devices.
Further, a circuit arrangement has been disclosed in the German Letters Patent No. 20 55 745, corresponding to U.S. Pat. No. 3,924,081, in which sub-central devices referred to as buffer memories are connected over information transmission paths individually associated thereto, i.e. are individually connected to the central control unit. The central control unit exhibits an input/output memory which comprises two list storages of which one serves for the input of information from the sub-central devices into the central control unit and the other serves the output of information from the central control unit to the sub-central devices. The individual information transmission paths provided in this known case per sub-central device, insofar as it is a matter of individual lines (as in the previously-specified known case), can have the advantage of more favorable transmission conditions because of the possibility of optimum line matching to the two ends of each of the lines, given which branchings, iterative networks and the like which are more disadvantageous in terms of transmission technology are eliminated. As soon as the individual information transmission paths are a matter of TDM channels, the individual connection of each of the buffer memories to the central control unit has the advantage of better supervision, particularly given a greater plurality of buffer memories, in view of the execution of the information transmission operations for data which, respectively coming from one of the buffer memories, are intended for one of the other buffer memories. However, this is conditioned in the known case in that the data must be intermediately stored in the central control unit memory.
It should be noted that all of the art citations herein are fully incorporated by the respective references thereto.